# Lecture 18 – Transistors and logic gates (Digital Systems)

## Transistors and logic gates

There are various circuit symbols for an n-type MOSFET – or in full, and n-channel enhancement mode metal-oxide-silicon field effect transistor.

We will generally use the simplest symbol, the one at the left. As the symbol suggests, the transistor consists of a piece of silicon (the channel) with terminals (the source and the drain) at the two ends, and separate connection to the gate, which is electrically isolated from the channel. Connecting the gate to a positive voltage with respect the the channel allows electrons to enter the channel at the source and to leave at the drain, so that a current flows in the transistor.

A simple model for the behaviour of such a transistor is that if the gate is connected to the positive power supply terminal (Vdd, typically +3.3V), the source and drain are connected together, but if it is connected to ground (0V), then they are not connected. We'll avoid situations where the gate is not connected to one of these two voltages.

We will also use another kind of transistor, the p-type.

The symbol with the little circle is not greatly liked by electronic engineers, but it's the one we shall use. The behavioural model we will adopt for the p-type is that if its gate is connected to ground, then the transistor conducts, and if it is connected to Vdd then it does not conduct.

We will (nearly) always design circuits in a style called CMOS (for complementary MOS) that contain equal numbers of n-type and p-type transistors. The simplest useful circuit is an inverter.

This circuit has one input at a and one output at z. If a is connected to ground, then the n-type transistor does not conduct, but the p-type does: this connects the output z to Vdd. On the other hand, if a is connected to Vdd, then it is the n-type transistor that conducts, connecting z to ground. We can make a truth table that summarises the behaviour of the circuit.

a z
0 1
1 0

It's worth noticing that in a steady state, only one of the transistors is conducting, so no quiescent current is drawn from the supply. Also, the gates of the transistors are electrically insulated from the supply, so no current is drawn from the input a in a steady state. Current does flow during transistions, because there is some capacitance between the gate and channel that must be charged or discharged when the gate voltage changes, and for a brief period both transistors will be partially turned on, allowing current to flow through them. Facts like this lead to the observation that the power dissipation of a CMOS logic circuit is proportional to the rate of state transitions.

Another important observation is that if the input a is not actually at the rails, but close to them, then that will be enough to fully turn off one transistor and fully turn on the other, and the output will be very close to the opposite rail. Despite the fact that a negligible current is drawn at the input, substantial current is available at the output. It is this amplifying behaviour of logic gates that lets us build large, complex assemblies of gates with many stages and have the whole thing behave in a digital way.

We can't do much with just an inverter! So let's next look at this design for a NAND gate.

In this circuit (as you see) there are two n-type transistors in series connecting the output z to ground, and two p-types in parallel connecting it to Vdd. Each input of the circuit, a or b, is connected to one of the n-types and one of the p types. We can analyse the behaviour of this circuit case by case, but the upshot is that if one or both of the inputs are grounded, then one or both of the p-types will conduct, driving the output high; and in these cases the two n-types are never both conducting, so there is no path from the output to ground. On the other hand, of both inputs are high, the two n-types both conduct, driving the output low, but the p-types do not conduct and the output is disconnected from Vdd. We call the function NAND, because the output is low only if both a and b are high. Here's the truth table:

a b z
0 0 1
0 1 1
1 0 1
1 1 0

The NAND gate seems a curious choice for our first useful gate, but it is actually a natural one, because it is simple, and because it shares with all simple CMOS gates the property of being anti-monotonic: as inputs change from 0 to 1, that can only make more of the n-type transistors in the bottom half of the gate conduct, and fewer of the p-types in the top half; and that can only cause the output, if it changes at all, to change from 1 to 0.

To get an AND gate, where the output is 1 exactly if both inputs are 1, we can follow the NAND gate with an inverter.

## CMOS gates in general

In general, a single CMOS gate has a network of n-type transistors connected between the output and ground, and a network of p-type transistors connected between the output and Vdd. Wherever n type transistors are connected in parallel, the corresponding p-type transistors are connected in series, and vice versa. For example, here is a design for an AND-OR-NOT gate:

In this circuit, the output z is connected to ground if either both a and b are high, or c is high (regardless of a and b). And z is connected to Vdd if both either a or b is low, and c is also low. In short,

z = ~((ab) ∨ c) = (~a ∨ ~b) ∧ ~c.

As a truth table,

a b c z
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 0

Complex gates like this are sometimes an efficient way of computing a Boolean function, but just NAND gates are enough to compute any function we might need. We can take any circuit in sum-of-products form (like either form of the majority function) and replace both the inner conjunctions and the outer disjunction with NAND gates. So for the more compact formula

f = (ab) ∨ (ac) ∨ (bc)

we obtain

f = NAND(NAND(a, b), NAND(a, c), NAND(b, c)).

This works essentially because of De Morgan's law, ¬(xy) = ¬ x ∨ ¬ y. Here is the corresponding circuit, consisting of just NAND gates:

## Questions

In the lectures, you used only p-type transistors in the upper part of a CMOS gate and the corresponding n-type transistors in the lower part. Can we mix them up in order to make a circuit that implements (a ∨ ¬b) ?

No, the rule for simple gates is that there is a pull-down network consisting of only n-type transistors, and a complementary pull-up network consisting of only p-types, with the gate of each transistor connected to an input of the gate. Consequently, the gate's function is anti-monotonic, and a ∨ ¬b cannot be implemented by a single gate. The best we can do is NANDa, b), which requires a NAND gate and an inverter. In a complex circuit, it's highly likely that ¬b would already be available, so the function would actually require only a single gate to be added.

It's reasonable to ask what would be a 'non-simple' gate, and there the added elements are pass-transistors, pairs of transistors containing an n-type and a p-type that either pass or block a signal. They don't help with implementing a ∨ ¬b, but if there's time I will mention them. There's a nice non-restoring implementation of XOR that uses two pairs of pass transistors and has a lower transistor count than the other implementations we've seen.