annotate lab4/regs.mli @ 0:bfdcc3820b32

Basis
author Mike Spivey <mike@cs.ox.ac.uk>
date Thu, 05 Oct 2017 08:04:15 +0100
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Mike Spivey <mike@cs.ox.ac.uk>
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1 (* lab4/regs.mli *)
Mike Spivey <mike@cs.ox.ac.uk>
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2 (* Copyright (c) 2017 J. M. Spivey *)
Mike Spivey <mike@cs.ox.ac.uk>
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3
Mike Spivey <mike@cs.ox.ac.uk>
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4 open Target
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5
Mike Spivey <mike@cs.ox.ac.uk>
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6 (* |init| -- initialise register state *)
Mike Spivey <mike@cs.ox.ac.uk>
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7 val init : unit -> unit
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8
Mike Spivey <mike@cs.ox.ac.uk>
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9 (* |is_free| -- test if register is free *)
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10 val is_free : reg -> bool
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11
Mike Spivey <mike@cs.ox.ac.uk>
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12 (* |get_regvars| -- reserve register variables *)
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13 val get_regvars : int -> unit
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14
Mike Spivey <mike@cs.ox.ac.uk>
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15 (* |alloc_reg| -- allocate any register *)
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16 val alloc_reg : unit -> reg
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17
Mike Spivey <mike@cs.ox.ac.uk>
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18 (* |get_reg| -- use specified register or allocate one if R_any *)
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19 val get_reg : reg -> reg
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20
Mike Spivey <mike@cs.ox.ac.uk>
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21 (* |reserve_reg| -- reserve a register *)
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22 val reserve_reg : reg -> unit
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23
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24 (* |release_reg| -- decrement reference count of register *)
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25 val release_reg : reg -> unit
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26
Mike Spivey <mike@cs.ox.ac.uk>
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27 (* |dump_regs| -- make one-line summary of register state *)
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28 val dump_regs : unit -> string
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29
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30
Mike Spivey <mike@cs.ox.ac.uk>
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31 (* Temps *)
Mike Spivey <mike@cs.ox.ac.uk>
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32
Mike Spivey <mike@cs.ox.ac.uk>
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33 (* |new_temp| -- allocate a temp with specified reference count *)
Mike Spivey <mike@cs.ox.ac.uk>
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34 val new_temp : int -> int
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35
Mike Spivey <mike@cs.ox.ac.uk>
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36 (* |inc_temp| -- increment refcount of a temp variable *)
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37 val inc_temp : int -> unit
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38
Mike Spivey <mike@cs.ox.ac.uk>
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39 (* |use_temp| -- use a temp variable *)
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40 val use_temp : int -> reg
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41
Mike Spivey <mike@cs.ox.ac.uk>
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42 (* |def_temp| -- define a temp variable *)
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43 val def_temp : int -> reg -> unit
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44
Mike Spivey <mike@cs.ox.ac.uk>
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45 (* |spill_temps| -- move any temps that use specified registers to safety *)
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46 val spill_temps : reg list -> unit
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47