comparison lab4/regs.mli @ 0:bfdcc3820b32

Basis
author Mike Spivey <mike@cs.ox.ac.uk>
date Thu, 05 Oct 2017 08:04:15 +0100
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-1:000000000000 0:bfdcc3820b32
1 (* lab4/regs.mli *)
2 (* Copyright (c) 2017 J. M. Spivey *)
3
4 open Target
5
6 (* |init| -- initialise register state *)
7 val init : unit -> unit
8
9 (* |is_free| -- test if register is free *)
10 val is_free : reg -> bool
11
12 (* |get_regvars| -- reserve register variables *)
13 val get_regvars : int -> unit
14
15 (* |alloc_reg| -- allocate any register *)
16 val alloc_reg : unit -> reg
17
18 (* |get_reg| -- use specified register or allocate one if R_any *)
19 val get_reg : reg -> reg
20
21 (* |reserve_reg| -- reserve a register *)
22 val reserve_reg : reg -> unit
23
24 (* |release_reg| -- decrement reference count of register *)
25 val release_reg : reg -> unit
26
27 (* |dump_regs| -- make one-line summary of register state *)
28 val dump_regs : unit -> string
29
30
31 (* Temps *)
32
33 (* |new_temp| -- allocate a temp with specified reference count *)
34 val new_temp : int -> int
35
36 (* |inc_temp| -- increment refcount of a temp variable *)
37 val inc_temp : int -> unit
38
39 (* |use_temp| -- use a temp variable *)
40 val use_temp : int -> reg
41
42 (* |def_temp| -- define a temp variable *)
43 val def_temp : int -> reg -> unit
44
45 (* |spill_temps| -- move any temps that use specified registers to safety *)
46 val spill_temps : reg list -> unit
47