Glossary (Digital Systems)

Copyright © 2024 J. M. Spivey
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(Application Binary Interface). A set of conventions about the use of registers and memory in calling subroutines, including which registers are used to pass parameters, and which must be saved and restored if they are used by a subroutine. By adhering to the same conventions, subroutines compiled from different languages can be made to operate together.
A set of logical connectives is adequate if it is able to express any Boolean function. In the lecture, I prove that the set {∧, ∨, ¬} is adequate, and then that {NAND} alone is also adequate. An exercise asks you to show that {XOR, ¬} is not adequate.
address space
A numbering system for memory locations. ARM-based microcontrollers (like most bigger machines) have a single address space containing both code and data. Some other microcontroller families have separate address spaces for code and data, in what is called a Harvard architecture.
addressing mode
In instructions that access memory, one of several rules for computing the address of the location to be accessed. For example, one addressing mode might obtain the address by adding the contents of two registers, and another might add a register and a small constant. CISC machines are characterised by more varied and more complex addressing modes than RISC machines.
The 64-bit variant of the Intel architecture used in PCs. So called because the instruction set extensions to support 64 bits was first introduced on chips designed by Advanced Micro Devices. Also known as x86_64.
assembly language
A symbolic representation of the machine code for a program.
The opposite of little-endian.
The simulation of a complex protocol by setting the values on GPIO pins under direct program control, with delay loops for timing. For example, serial communications require timings that are more precise that can be achieved by bit-banging, unless the processor is doing nothing else.
callee-save register
In an ABI, a register whose value must be preserved by a subroutine, and restored before the subroutine returns to whatever value it had before the call. On ARM Cortex-M machines, the ABI defines registers r4--r7 (and, less importantly, r8--r11) to be callee-save.
calling convention
(A near-synonym for ABI). The convention that determines where arguments for a subroutine are to be found, and where the result is returned.
(Complex Instruction Set Computer) The opposite of RISC.
condition codes
Four bits, N, Z, V and C, in the processor status word that indicate the result of a comparison or other arithmetic operation. Briefly, N indicates whether the result of the operation was negative, Z indicates whether it was zero, C is the value of the carry-out bit from the ALU, and V indicates whether the operation overflowed, yielding a result that was different in sign from what could be predicted from the inputs to the operation. A comparison is treated like a subtraction as far as setting the condition codes is concerned. After the condition codes have been set, a subsequent conditional branch instruction can test them, and make a branch decision based on a boolean combination of their values. All ten arithmetic comparisons (equal, not-equal, and less-than, less-than-or-equal, greater-than, and greater-than-or-equal for both signed and unsigned representations) can be represented in this way. When a process is interrupted, the condition codes must be saved and restored as part of the processor state, in case the interrupt came between a comparison and a subsequent conditional branch.
(Cortex Mobile Software Interface Standard).
cross compiling
Using a compiler on one machine to translate programs into binary code for a different machine. In the course, we will use a PC running Linux to compile code the the micro:bit, an ARM-based device: this is convenient because the micro:bit itself is too small to run a compiler and other tools.
crystal oscillator
An electronic oscillator with a highly stable frequency, determined by piezo-electric vibrations in a quartz crystal. Most microcontroller chips contain the active parts of a crystal oscillator, requiring only the addition of an external crystal and a couple of loading capacitors in order to form a stable oscillator for the system clock. The micro:bit has a 16MHz crystal that determines the clock frequency for the nRF51822.
flash memory
see Read-only memory.
(General-Purpose Input/Output). A peripheral interface that provides direct access to pins of the microcontroller chip. Pins may be configured as inputs or outputs, and interrupts may be associated with state changes on certain input pins. On the micro:bit, the LEDs and pushbuttons are connected to GPIO pins.
(Inter-Integrated Circuit Bus). A synchronous serial communications standard widely used for internal communication within a computer system, especially between a microcontroller and peripherals implemented as integrated circuits, with a bandwidth of 100kbaud or higher. Apart from power and ground, only two wires are required for a bus connecting many chips: the data line SDA and the clock line SCL. Both are active-high with pullup resistors, and are driven by each device using an open-collector (open-drain) output, acheiving effectively wired-or logic; this makes bus arbitration fairly simple. Each device on an I2C bus has a distinct, seven-bit address, and ignores transactions that do not begin with its own address, so that multiple slave devices can share the bus.
leaf routine
A subroutine that uses only a few registers and calls no others. On the Cortex-M0, such a routine can use only registers r0 to r3. The code for a leaf routine need not establish a stack frame or save its return address in memory, but can leave it where it arrives (in register lr) and return directly (using the instruction bx lr). This is an important optimisation, particularly for programs that contain many small subroutines for the sake of data abstraction.
linker script
A text, written in a specialised language, that describes the layout in memory of a program. Compilers typically divide their output into four named sections: text for the program code and embedded constants, data for statically allocated data that has a specified initial value other than zero, rodata for initialised data that is constant, and bss for data that is statically allocated but can initially be filled with zeroes. The linker script may add another section for the program's stack. For microcontrollers, a linker script is needed that puts the text and rodata in Flash, and lays out the RAM so that stack and bss are in separate areas, with the data copied into its own part of RAM from an image held in Flash.
link register
On ARM processors, a register (r14) in which the program counter value is saved by the instructions bl and blx that call a subroutine. The subroutine can return by branching to this address with the instruction bx lr, or can save the value on the stack (with push {..., lr}) and later return by restoring the same value back into the program counter (with pop {..., pc}).
A computer with byte-addressed memory is little-endian if the least significant byte of a multi-byte integer in memory is the one with the lowest address, the same as the address of the word itself. Thus on the ARM as conventionally configured, if the integer 0x1a2b3c4d is stored at address 0x1000, then byte 0x1000 in the memory contains 0x4d, byte 0x1001 contains 0x3c, byte 0x1002 contains 0x2b, and byte 0x1003 contains 0x1a. At first, this seems counter-intuitive, until you realise that the real problem is the way we write numbers in everyday life, with the digit worth 100 at the end, and the one worth 10n-1 at the beginning.
low register
On Cortex-M processors, one of the general-purpose registers r0--r7 that can be used in most instructions. Of the remaining, high registers, the stack pointer r13, the link register r14, and the program counter r15 serve special purposes, and are accessed implicitly by certain instructions. The other high registers, r8--r11 are accessible using only a very few instructions, and are little used.
map file
A report produced by the linker, showing what library modules were included in the program, and for each module where in the program image it has been put.
memory management unit
A processor component that comes between the CPU and the memory, and efficiently translates virtual addresses generated by the running process into physical addresses denoting a specific storage location. By varying the parameters of the translation, an operating system can arrange that different processes exist in distinct, separate address spaces. Microcontrollers commonly lack an MMU, and all processes then run in the same address space, and must be carefully written not to interfere with each other.
A single integrated circuit that contains a microprocessor together with some memory (usually both RAM for dynamic state and ROM for storing a persistent program) and peripheral interfaces.
An integrated circuit that contains a complete CPU.
An instruction that has no effect, but takes a little time (perhaps one cycle) to execute. In Thumb code, the nop instruction is a synonym for mov r8, r8, and does indeed take one cycle on Cortex-M0.
(Nested Vector Interrupt Controller). An ARM processor component that is able to assign priorities to external interrupts (as opposed to those generated by internally by the processor) and control the servicing of interrupts. As the name indicates, it is able to cope with nested interrupts, where servicing of one interrupt is itself interrupted by another with higher priority. Note that, according to ARM conventions, higher priorities are indicated by lower numbers.
open-collector output
open-drain output
A gate output that consists of a single transistor connected between the output and ground. When the gate is active, it can sink current and pull the output low, but when it is inactive it does not prevent other outputs connected to the same wire from pulling it low. Open collector outputs are commonly used with a separate pull-up resistor connected between the wire and the positive power rail.
pre-emptive scheduling
A form of process scheduling where a process may be suspended when it has run for a certain time, or a process with higher priority becomes ready. Without pre-emptive scheduling, processes are only suspended when they wait for an event.
program counter
A register that contains the address of the next instruction to be executed. Because of pipelining, on ARM Cortex-M machines, reading the program counter yields a value that is 4 bytes greater than the address of the current instruction.
PC-relative addressing
An addressing mode that involves adding a fixed offset to the value of the program counter in order to form an address. On ARM, a large constant that does not fit in the immediate field of an instruction can be loaded into a register using a PC-relative load instruction. The assembler generated such instructions, and automatically lays out a table of literal values, when a programmer uses the syntax ldr rn, =const.
RC oscillator
A cheap alternative to a crystal oscillator. A capacitor (C) charges through a resistor (R), until it reaches a threshold voltage, at which point a transistor is switched on to discharge it again, creating an oscillation. The frequency of the oscillation is determined by the time constant RC; it is rather less stable than a crystal oscillator, because both the resistor and the capactor tend to have values that vary significantly with temperature.
(Reduced Instruction Set Computer). A style of computer design where there are multiple, identical registers, arithmetic instructions that operate between registers, and separate load and store instructions with a limited set of addressing modes.
(Read-Only Memory). A form of storage whose contents are non-volatile (are not lost when the power is off) but cannot be changed under program control. Modern ROM is usually EEPROM – Electrically Erasable Programmable Read Only Memory, and can be changed electrically, and even under control of a program running on the microcontroller, but using special peripheral registers and not the normal store instructions. Flash memory is a modern, super-compact implementation of EEPROM, but for our purposes it does exactly the same job. We will modify the contents of the micro:bit's flash memory by downloading programs, but we will probably not be writing programs that change the contents of the flash memory.
(Small-scale integration). An implementation of combinational and sequential logic using packaged integrated circuits that each contain a handful of gates or a couple of flip-flops. The opposite of LSI or VLSI technology.
stack pointer
A register sp that holds the address of the most recent occupied word of the subroutine stack. On ARM, as on most recent processors, the subroutine stack grows downwards, so that the sp holds the lowest address of any occupied work on the stack.
three-state logic
A convention where multiple outputs can share a single wire; those outputs that are not currently driving the wire high or low must be put into a third, high impedance state so as not to interfere with others.
An alternative instruction encoding for the ARM in which each instruction is encoded in 16 rather than 32 bits. The advantage is compact code, the disadvantage that only a selection of instructions can be encoded, and only the first 8 registers are easily accessible. In Cortex-M microcontrollers, the Thumb encoding is the only one provided.
two's-complement representation
A representation for signed numbers, common to all recent computer systems, where negating a number involves complementing each bit and then adding 1. An advantage of two's-complement representation is that the same adder circuit can be used for both signed and unsigned arithmetic, though the criteria for detecting overflow are different in the two cases.
(Universal Asynchronous Receiver/Transmitter). A peripheral interface that is able to send and receive characters serially, commonly used in the past for communication between a computer and an attached terminal. It is commonly used in duplex mode, with the transmitter of one device connected to the receiver of the other with one wire, and the receiver of the one connected to transmitter of the other with a different wire. The asynchronous part of the name refers to the fact that the transmitter and receiver on each wire do not share a common clock, but rely instead on the signalling protocol and precise timing to achieve synchronisation.
wired-or logic
A bus convention where a wire carries a 1 bit if any device connected to it is transmitting a 1. This is commonly implemented by having each device connected to the bus with an open-collector output, and wiring a pullup resistor from the wire to the positive power rail. Devices then signal a 1 by pulling the wire low.