Syllabus and synopsis

Copyright © 2017–2023 J. M. Spivey
Revision as of 23:12, 11 January 2022 by Mike (talk | contribs) (→‎Synopsis)
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)
Jump to navigation Jump to search

Overview

In this course, participants will learn about the building blocks of computer hardware and software by studying the design of a sequence of simple embedded systems, including understanding how the hardware works, and how it can be programmed at a low level, using assembly language on the bare hardware, and at a high level, using C code and a process scheduler.

Learning outcomes

Following the course, participants will be able to

  • Explain the functioning of computer hardware at the gate level and architectural level.
  • Understand the low-level mechanisms that support programming in a high-level language.
  • Design programs that interact with the hardware of the processor and I/O devices.
  • Interpret IC datasheets in order to drive simple I/O devices.

Syllabus

Simple design of combinational and sequential circuits; standard design elements.
Data representations and computer arithmetic.
Register transfer level design of a simple microprocessor.
Programming at the machine level: registers, instructions, memory addressing, subroutines, interrupts.
Rôle of assemblers, compilers and linkers.
Simple operating system services: processes, device drivers.

XKCD #1988

Synopsis

Hilary Term

Programming at the machine level: the programmer's model.

Number representations and computer arithmetic.

Control structures and conditional branching.

Memory addressing, arrays, records and pointers.

Programming I/O devices: device registers, GPIO, UART.

Interrupt control and asynchronous events.

Programming with a simple operating system. Processes and message passing.

Implementing the operating system: context switches, process queues.

Trinity Term

Combinational and sequential circuits. Logic gates in CMOS.

Architectural components: ALU, register file, control unit.

Register-transfer level design of a simple implementation scheme.