Thunder instruction set

Integer operations

ADD/SUB/MUL reg, reg, reg/imm          Arithmetic operations
AND/XOR/OR reg, reg, reg/imm           Logical operations
LSH/RSH/RSHu/ROR reg, reg, reg/imm     Shifts
MOV reg, reg/imm/lab                   Moves
NEG reg, reg                           Unary minus
NOT reg, reg                           Bitwise not

Floating point

ADDf/SUBf/MULf/DIVf freg, freg, freg   Float arithmetic
ADDd/SUBd/MULd/DIVd freg, freg, freg   Double arithmetic
NEGf/NEGd freg, freg                   Negation
MOV freg, freg                         Single precision move
MOVq freg, freg                        Double precision move
ZEROf/ZEROd freg                       Set register to zero

Conversions

CONVif freg, reg                       Integer to float
CONVid freg, reg                       Integer to double
CONVfi reg, freg                       Float to integer
CONVdi reg, freg                       Double to integer
CONVfd freg, freg                      Float to double
CONVdf freg, freg                      Double to float
CONVis reg, reg                        Integer to short

Comparisons and branches

EQ/GE/GT/LE/LT/NE reg, reg, reg/imm    Integer comparisons with Boolean result
GEu/GTu/LEu/LTu reg, reg, reg/imm      Unsigned comparisons with Boolean result
EQf/GEf/GTf/LEf/LTf/NEf reg, freg, freg     Float comparisons, Bool result
EQd/GEd/GTd/LEd/LTd/NEd reg, freg, freg     Double comparisons, Bool result

BEQ/BGE/BGT/BLE/BLT/BNE reg, reg/imm, lab   Integer conditional branches
BGEu/BGTu/BLEu/BLTu reg, reg/imm, lab       Unsigned conditional branches
BEQf/BGEf/BGTf/BLEf/BLTf/BNEf freg, freg, lab    Float conditional branches
BNGEf/BNGTf/BNLEf/BNLTf freg, freg, lab          Negated float branches
BEQf/BGEf/BGTf/BLEf/BLTf/BNEf freg, freg, lab    Double conditional branches
BNGEf/BNGTf/BNLEf/BNLTf freg, freg, lab          Negated double branches

(Note that BNGEf is not equivalent to BLTf because they treat have a different meaning when one or both operands are NaN.)

JUMP reg/lab                           Unconditional branch

Loads and stores

LDW/STW/LDS/STS/LDB/STB reg, ...       Integer loads and stores
LDSu/LDBu reg, ...                     Unsigned loads
LDW/STW freg, ...                      Floating-point load and store
LDQ/STQ freg, ...                      Double load and store

Addressing modes:

    ...  reg/imm                       reg or imm    
    ...  reg1, reg2/imm                reg1+reg2 or reg1+imm
    ...  reg1, reg2, scale             reg1 + reg2<<scale

Procedure call

PREP imm                               Prepare call (no. of arguments)
ARG reg/imm                            Push arguments from right to left
CALL reg/addr                          Execute call

GETARG reg, imm                        Fetch argument into register